Intel’s Nova Lake generation is presumably still in development, but that hasn’t stopped the rumor mill from continuing to break down the “Core Ultra 400” CPUs.
For almost a decade, AMD has dominated the CPU market almost at will with its Ryzen processors, while Intel has slipped into a veritable crisis. With the upcoming Nova Lake generation, the Santa Clara-based company wants to strike back, as far as we can gather from the rumor mill.
Leaker Haze2K1 now provides insight into the configurations that are supposed to make the series, presumably called “Core Ultra 400,” a success. The previously rumored 52 cores are mentioned again here.
bLLC apparently limited to premium segments
According to the leaker, the flagship CPU of the Nova Lake generation will have a total of 16 P(erformance) cores, 32 E(fficiency) cores, and 4 L (ow)-P(ower)-E(fficiency) cores. The target clock speeds are still unclear.
According to Haze2K1, the monster CPU with 52 cores will be joined by three other configurations in the premium segment of the new Intel generation:
- 14 P-, 24 E-, and 4 LPE-cores (total: 42 cores)
- 8 P-, 16 E-, and 4 LPE cores (total: 28 cores)
- 8 P-, 12 E-, and 4 LPE cores (total: 24 cores)
Nova lake-s with big last level cache:
16p 32e 4lpe
14p 24e 4lpe
8p 16e 4lpe
8p 12e 4lpe— Haze (@Haze2K1) December 17, 2025
Link to Twitter content
Other processors with smaller core counts are also likely to be included in the range, which will be positioned in the budget and mid-range segments.
Only the four configurations mentioned, which are expected to run on Core Ultra 9 and Core Ultra 7, are to be equipped with a feature that is intended to be the answer to AMD’s successful 3D V-Cache.
This refers to “bLLC” technology, which stands for “Big Last Level Cache.” According to 3DCenter, Intel is excluding the Core Ultra 5 series from bLLC. Previously, via wccftech that only processors with an unlocked multiplier will have access to the larger cache.
- The actual size of this new cache is still unclear. According to current speculation, up to 144 MB of additional L3 cache per compute tile should be possible.
- For comparison: Depending on the model, AMD provides between 64 and 96 MB of additional L3 cache.
